It is known to provide data processing systems incorporating memories with self-testing mechanisms, sometimes termed built-in self-test (BIST), such that when the memory circuits have been fabricated they may conduct a self-test or series of self-tests to determine if there are any memory defects present that would indicate that the circuit should be rejected. It is important that memory circuits should be highly reliable and that defective circuits should be effectively identified. As memory sizes increase, the proportion of the die being taken up by the memory is also increasing and, furthermore, the high transistor density within memory means that the defect density of these memories is becoming increasingly significant.
The type of defect that can arise may vary significantly from design to design fabrication processes applied to the same design. For this reason, self test methodologies are normally selected and tuned to a particular design and fabrication technique by the manufacturer concerned. A manufacturer will typically have their own preferred test methodology that experience has told them is well suited to their particular environment to identify defective memories. The test methodology adopted by one manufacturer may well not work well for another manufacturer.
It will be appreciated that self-test circuits whilst necessary to ensure a memory has been correctly fabricated, do represent a circuit area overhead that should be desirably reduced. The self-test circuits are typically used when an integrated circuit is manufactured but thereafter are not used during the normal operation of the integrated circuit.